1. Field of the Invention
The present invention relates to a flip-chip package substrate and a method for fabricating the same, more particularly, to a structure of a flip chip substrate without plating through holes having improved density of circuit layout and a manufacturing method of a flip-chip package substrate to simplify the process.
2. Description of Related Art
In the development of electronics, the design trend of electronic devices is towards to multifunction and high-performance. Thus, high-density integration and miniaturization are necessary for a semiconductor package structure. On the ground aforementioned, the doublelayer circuit boards providing active components, passive components, and circuit connection, are being replaced by the multilayer circuit boards. The area of circuit layout on the circuit board increases in a restricted space by interlayer connection when meeting the requirement of high-density integration.
In the conventional semiconductor device structure, a semiconductor chip is attached on top of a substrate and then processed in wire bonding or a chip is connected to a substrate by a flip chip package. Further, solder balls are disposed on the side of the substrate that does not have semiconductor chip attached thereto so as to connect with external electronic devices. Although more connecting ends are provided, the performance of electronic devices cannot be enhanced but is in fact restricted, owing to the over-long path of circuit and resulting high resistance for high frequency operation.
In the conventional method for manufacturing a structure of a package substrate, a core-board is provided first, and then the structure of the inner circuit layer is accomplished by drilling, electroplating, plugging holes, forming circuits and so on. Subsequently, a multilayer package substrate is accomplished by circuit build-up layer technology. One of methods for manufacturing a multilayer circuit board of circuit build-up layers is shown in FIGS. 1A to 1E. As shown in FIG. 1A, a core-board 11, comprising a core layer 111 of determined thickness and a first circuit layer 112 on the surface of the core layer 111, is provided first. At the same time, plural plating through holes 113 are formed in the core layer 111. Accordingly, the first circuit layers 112 on the top surface and the back surface of the core layer 111 are connected to each other through the plating through holes 113. As shown in FIG. 1B, a circuit build-up process is performed on the core-board 11 to dispose a dielectric layer 12 on the surface of the core-board 11, wherein plural vias 13 are formed in the dielectric layer 12 to connect with the first circuit layer 112. As shown in FIG. 1C, a conductive layer 14 is formed on the surface of the dielectric layer 12 by electroless plating or sputtering, and a resistive layer 15 is formed on the surface of the conductive layer 14. The resistive layer 15 is patterned and plural openings 150 are formed to expose the part surface of the conductive layer 14. As shown in FIG. 1D, a patterned second circuit layer 16 and a conductive blind via 13a are formed, wherein the second circuit layer 16 can be connected to the first circuit layer 112 through the conductive via 13a. Then, the resistive layer 15 and the partial conductive layer 14 covered by the resistive layer are removed. Thereby, a first circuit build-up layer 10a is accomplished. As shown in 1E, a second circuit build-up layer 10b can be formed on the surface of the first circuit build-up layer 10a by the above process and a multilayer package substrate 10 is accomplished.
In the aforementioned method of providing a core-board, then accomplishing the inner structure by drilling, electroplating, plugging holes, forming the circuit and so on, and subsequently, realizing a multilayer package substrate by circuit build-up layer technology, some drawbacks exist such as low density of circuit layout, excessive layers, long circuit path, and high resistance. Thereby, the electric property is poor in high frequency operation; in addition, the excessive layers result in the complex manufacturing processes and high manufacturing cost.